About the Course

Need for Digital Logic Design

Introduction to Different Number System and their Conversions - Part 1

Introduction to Different Number System and their Conversions - Part 2

Introduction to Different Number System and their Conversions - Part 3

Introduction to Different Number System and their Conversions - Part 4

Introduction to Different Number System and their Conversions - Part 5

Introduction to Various Codes in Digital System - Part 1

Introduction to Various Codes in Digital System - Part 2

Introduction to Various Codes in Digital System - Part 3

Introduction to Boolean Algebra and Boolean Theorems - Part 1

Introduction to Boolean Algebra and Boolean Theorems - Part 2

Introduction to Boolean Algebra and Boolean Theorems - Part 3

Minimization of Boolean Expressions by using Theorems - Part 1

Minimization of Boolean Expressions by using Theorems - Part 2

Minimization of Boolean Expressions by using Theorems - Part 3

Minimization of Boolean Expressions by using Theorems - Part 4

Minimization of Boolean Expressions by using Theorems - Part 5

Canonical Forms in Digital Logic - SOP Part 1

Canonical Forms in Digital Logic - SOP Part 2

Canonical Forms in Digital Logic - POS Part 1

Canonical Forms in Digital Logic - POS Part 2

Implementation of Boolean Functions with NAND and NOR Gates - Part 1

Implementation of Boolean Functions with NAND and NOR Gates - Part 2

Implementation of Boolean Functions with NAND and NOR Gates - Part 3

Implementation of Boolean Functions with NAND and NOR Gates - Part 4

Implementation of Boolean Functions with NAND and NOR Gates - Part 5

Introduction to Karnaugh Map

2 and 3 Variable K-Map Simplification with Examples - Part 1

2 and 3 Variable K-Map Simplification with Examples - Part 2

2 and 3 Variable K-Map Simplification with Examples - Part 3

2 and 3 Variable K-Map Simplification with Examples - Part 4

2 and 3 Variable K-Map Simplification with Examples - Part 5

2 and 3 Variable K-Map Simplification with Examples - Part 6

4 Variable K-Map Simplification with Examples - Part 1

4 Variable K-Map Simplification with Examples - Part 2

4 Variable K-Map Simplification with Examples - Part 3

K-Map Simplification for POS Expressions - Part 1

K-Map Simplification for POS Expressions - Part 2

K-Map Simplification for POS Expressions - Part 3

Quine-McCluskey Method to Simplify Digital Logic - Part 1

Quine-McCluskey Method to Simplify Digital Logic - Part 2

Quine-McCluskey Method to Simplify Digital Logic - Part 3

Quine-McCluskey Method to Simplify Digital Logic - Part 4

Design of Binary Adder Part-1

Design of Binary Adder Part-2

Design of Binary Adder Part-3

Design of Multibit Adder Part-1

Design of Multibit Adder Part-2

Design of Binary Subtractor Part-1

Design of Binary Subtractor Part-2

Design of Binary Subtractor Part-3

Design of Binary Subtractor Part-4

Design of Parity Circuits

Design of Unsigned Multiplier Part-1

Design of Unsigned Multiplier Part-2

Design of Signed Multiplier Part-1

Design of Signed Multiplier Part-2

Design of Signed Multiplier Part-3

Design of Signed Multiplier Part-4

Design of Signed Multiplier Part-5

Design of Magnitude Comparator Part-1

Design of Magnitude Comparator Part-2

Design of Magnitude Comparator Part-3

Design of Encoder Part-1

Design of Encoder Part-2

Design of Decoder Part-1

Design of Decoder Part-2

Design of Decoder Part-3

Design of Multiplexer Part-1

Design of Multiplexer Part-2

Design of Multiplexer Part-3

Design of Demultiplexer Part-1

Design of Demultiplexer Part-2

Design of Shifters 1 Part-1

Design of Shifters 1 Part-2

Design of Shifters 1 Part-3

Design of Shifters 2 Part-1

Design of Shifters 2 Part-2

Design of Sequential Circuits: SR Latch and Flip Flop - Part 1

Design of Sequential Circuits: SR Latch and Flip Flop - Part 2

Design of Sequential Circuits: JK Flip Flop

Design of Sequential Circuits: D & T Latches and Flip Flops - Part 1

Design of Sequential Circuits: D & T Latches and Flip Flops - Part 2

Design of Sequential Circuits: Registers - Part 1

Design of Sequential Circuits: Registers - Part 2

Design of Sequential Circuits: Registers - Part 3

Design of Sequential Circuits: Asynchronous Counters - Part 1

Design of Sequential Circuits: Asynchronous Counters - Part 2

Design of Sequential Circuits: Synchronous Counters - Part 1

Design of Sequential Circuits: Synchronous Counters - Part 2

Design of Sequential Circuits: Synchronous Counters - Part 3

Design of Sequential Circuits: Synchronous Counters - Part 4

Design of Sequential Circuits: Synchronous Counters - Part 5

Design of Sequential Circuits: Synchronous Counters - Part 6

Finite State Machines - Mealy State Sequential circuits - Part 1

Finite State Machines - Mealy State Sequential circuits - Part 2

Finite State Machines - Mealy State Sequential circuits - Part 3

Finite State Machines - Mealy State Sequential circuits - Part 4

Finite State Machines - Moore State Sequential circuits - Part 1

Finite State Machines - Moore State Sequential circuits - Part 2

Finite State Machines - Moore State Sequential circuits - Part 3

Finite State Machines - Moore State Sequential circuits - Part 4

Memory and Its Types - Part 1

Memory and Its Types - Part 2

Addressing of Memory - Part 1

Addressing of Memory - Part 2

Digital Design Using PROM - Part 1

Digital Design Using PROM - Part 2

Digital Design Using PLA - Part 1

Digital Design Using PLA - Part 2

Digital Design Using PLA - Part 3

Digital Design Using PLA - Part 4

Digital Design Using PLA - Part 5

Digital Design Using PAL - Part 1

Digital Design Using PAL - Part 2

Digital Design Using PAL - Part 3

Digital Design Using PAL - Part 4

Digital Design Using PAL - Part 5

Introduction to CPLD and FPGA 1 - Part 1

Introduction to CPLD and FPGA 1 - Part 2

Introduction to CPLD and FPGA 2 - Part 1

Introduction to CPLD and FPGA 2 - Part 2

VLSI Design Flow 1 - Part 1

VLSI Design Flow 1 - Part 2

VLSI Design Flow 1 - Part 3

VLSI Design Flow 2 - Part 1

VLSI Design Flow 2 - Part 2

VLSI Design Flow 3 - Part 1

VLSI Design Flow 3 - Part 2